Module EC-21

Hardware Verification, FPGA and SoC Design

What happens to a digital design after it has been written and before anyone can build it. A testbench good enough to be trusted and the assertions and coverage that say when it is finished, the tools that turn source into a configured device, the timing analysis that decides whether it will actually run at the stated speed, the two hardest structural problems in synchronous design, the test logic a designer must put in so the manufactured part can be tested at all, and the flow and buses of a system assembled largely from somebody else's blocks.