Module S4-4
Digital System Design
From Boolean algebra to working hardware: logic minimization, combinational and sequential design, then Verilog HDL through to synthesis and FPGA. Folds in the Digital System Design lab as code-and-simulate checkpoints.
5 topics ~47 h estimated learning time5 of 5 topics in a reviewed syllabus
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- S4-4.1 Logic Simplification & Realization
Core · 9 hCommon in syllabi
- S4-4.2 Combinational Design
Core · 9 hCommon in syllabi
- S4-4.3 Sequential Logic Design
Core · 10 hCommon in syllabi
- S4-4.4 Verilog HDL: Gate & Dataflow Modelling
Core · 9 hCommon in syllabi
- S4-4.5 Verilog: Behavioral Modelling & Synthesis
Core · 10 hCommon in syllabi