EC-21.6 Design for Test: Scan, Built-In Self-Test and Fault Coverage
You can explain why a manufactured chip cannot be tested through its functional inputs alone, describe how scan insertion makes every register controllable and observable, and interpret a fault coverage figure.
Before:S4-4. Digital System DesignPE2-1. CMOS Analog and Digital IC DesignUnlocks:EC-25. Semiconductor Test, Packaging and Reliability
This is the designer's half of testing. A finished chip has a few hundred pins and many millions of internal nodes, and no sequence of ordinary inputs will exercise them all in an acceptable time. The answer is to build extra logic that turns every register into something the tester can write and read directly, which costs area and speed and is nevertheless universal. What the tester then does with it is the next module's subject.
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Why functional test does not scale, and what controllability and observability mean
Reaching an internal node through ordinary inputs may take thousands of cycles, and seeing the result may be impossible. Design for test exists to make every state element directly reachable and directly visible instead.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseThe stuck-at fault model, and why such a crude model works
Modelling every possible defect as a node held permanently high or low is plainly wrong in detail and catches most real manufacturing defects in practice. The justification is empirical rather than theoretical.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseScan insertion: turning registers into a shift register for test
Adding a multiplexer to every flip-flop lets the whole design be loaded and unloaded serially in test mode. The cost is area and a little speed, and essentially every digital chip pays it.
NPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi) · CourseAutomatic test pattern generation, and what fault coverage means
A tool computes the input patterns needed to expose each modelled fault and reports the fraction it can reach. A coverage figure below the target points at logic that no pattern can exercise, which is a design problem.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseBuilt-in self-test, especially for memories
Rather than shifting patterns in from outside, a small generator and checker on the chip can test a block at full speed. Memories are almost always tested this way because their regular structure makes the generator simple.
Boundary scan, and testing the board rather than the chip
A standard four-wire interface lets a tester drive and observe every pin of every chip on an assembled board, which finds unsoldered joints and shorts. It is also how many parts are programmed and debugged.
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