EC-21.5 Crossing Clock Domains, and Getting Reset Right
You can explain metastability in terms of the flip-flop's own behaviour, choose the right synchroniser for a single bit and for a multi-bit value, and design a reset that releases cleanly in every clock domain of a system.
Before:S4-4. Digital System DesignPE2-1. CMOS Analog and Digital IC DesignUnlocks:EC-25. Semiconductor Test, Packaging and Reliability
These are the two failures that survive every simulation and appear months later in the field, at a rate of once a week, on one unit in fifty. Neither is difficult once seen clearly, and both are catastrophic when handled by instinct. A two-flip-flop synchroniser and an asynchronously asserted, synchronously released reset are small pieces of code that a hardware engineer is expected to be able to write from memory.
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Metastability: what a flip-flop does when setup and hold are violated
A flip-flop clocked while its input is changing can sit between the two logic levels for an unbounded time before settling arbitrarily. The behaviour is statistical rather than deterministic, which is exactly why simulation never shows it.
NPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee) · CourseThe two-flip-flop synchroniser, and the mean time between failures it buys
Chaining a second register gives the first one time to settle, and the improvement is quantified as a mean time between failures that depends on the clock rate and the data rate. Three stages are used where that figure is not long enough.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseWhy a multi-bit value cannot be synchronised bit by bit
Independent synchronisers settle at independent moments, so a counter crossed bit by bit can be sampled as a value it never held. This is the single most common serious mistake in multi-clock design.
Handshakes, Gray codes and asynchronous first-in-first-out memories
The three standard answers are to pass one bit and hold the data still, to encode so that only one bit changes at a time, or to use a memory built for the purpose. Each has a throughput and latency cost worth knowing.
NPTEL: System Design through Verilog (IIT Guwahati) · CourseReset: asynchronous assertion, synchronous release, and reset domains
A reset that is removed at an arbitrary moment can violate recovery timing and leave part of a design in a different state from the rest. The standard shape asserts immediately and releases in step with each clock.
NPTEL: System Design through Verilog (IIT Guwahati) · CourseChecking crossings automatically, because review will not find them all
Tools exist that identify every signal crossing between clocks and verify that a recognised structure protects it. On a design with several clocks this is not optional, because the number of crossings exceeds what anybody can enumerate by hand.
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