EC-21.1 SystemVerilog, and a Testbench You Can Trust
You can write a self-checking testbench with a driver, a monitor and a reference model, generate constrained random stimulus, and explain why a testbench that a person has to watch is not a testbench.
Before:S4-4. Digital System DesignPE2-1. CMOS Analog and Digital IC DesignUnlocks:EC-25. Semiconductor Test, Packaging and Reliability
Writing the design is the smaller half of the work; proving it correct is the larger one, and it is a separate skill with its own language features. The change that matters is self-checking: a test that prints waveforms needs an expert to read it, while a test that compares against a reference model and says pass or fail can be run by a machine ten thousand times overnight. Everything else in this module depends on having that.
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What SystemVerilog adds for verification, and why it is a separate skill
Interfaces, classes, randomisation and functional coverage exist for the person testing a design rather than the person writing it. Treating verification as a second job with its own tools is the single largest difference between student and industrial practice.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseThe shape of a testbench: driver, monitor, scoreboard and reference model
Separating the thing that applies stimulus, the thing that observes, and the thing that decides correctness makes each replaceable. The same structure scales from a small block to a whole system, which is why it is worth adopting early.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseSelf-checking tests, and why a waveform is not a result
A test whose output is a picture requires a person to interpret it, which limits you to as many tests as you have patience for. A test that returns pass or fail can be run automatically on every change, which is what makes regression possible.
Constrained random stimulus, and directed tests for the cases you already fear
Random input with legality constraints finds combinations nobody thought to write, and directed tests cover the corners you already know about. Real verification uses both, and knowing which one found a bug tells you something about your assumptions.
NPTEL: VLSI Design Verification and Test (IIT Guwahati) · CourseSimulation, and what a simulator cannot tell you
A simulator runs your design against your model of the world, so anything wrong with the model is invisible. Timing, physical effects and misread specifications all pass simulation happily, which is why later topics exist.
NPTEL: System Design through Verilog (IIT Guwahati) · CourseRegression: running everything again, automatically, on every change
The value of a test suite is realised only when it runs without being asked. A design with a hundred tests that nobody runs is in worse shape than one with ten that run on every commit.
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