EC-21.3 Getting a Design onto an FPGA: Synthesis, Placement and Routing

Work through these

• What is inside the part: lookup tables, flip-flops, memories and multipliers

  A field-programmable device is a fixed array of small resources plus a configurable interconnect between them, not a blank slate. Every synthesis decision is an attempt to express your logic in those resources.

  NPTEL: Digital System Design with PLDs and FPGAs (IISc Bangalore) · Course

• Synthesis: inference, and the code shapes that produce the hardware you wanted

  The tool infers a memory, a multiplier or a counter from the shape of your code, and a small difference in how a reset is written can turn a block memory into thousands of registers. Reading the inference report is how you find out which happened.

  NPTEL: Digital System Design with PLDs and FPGAs (IISc Bangalore) · Course

• Placement and routing, and why the interconnect is the scarce resource

  Deciding where each piece of logic sits and how the wires between them are threaded is the slow part of the flow, and congestion in the wiring usually limits a design before the logic runs out. That is the opposite of most beginners' expectations.

  NPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi) · Course

• Reading a utilisation report, and what it means to not fit

  The report says how much of each resource type is used, and a design can fail while three of the four are nearly empty. Knowing which resource ran out points directly at what to change.

• The bitstream, configuration and programming the device

  The output of the flow is a configuration file that sets every lookup table and switch in the part, loaded at power-up from a memory or a cable. Where that file lives and how it is protected is a product decision as much as a design one.

  NPTEL: Digital System Design with PLDs and FPGAs (IISc Bangalore) · Course

• Debugging inside the device, and the logic analyser you can synthesise

  Once a design is in the part, the signals inside it are invisible unless you deliberately built a way to see them. An embedded analyser core costs resources and is usually the fastest way to find out what is happening.