EC-21.7 From FPGA to ASIC: The Flow, the Buses, and Somebody Else's IP
You can lay out the steps from a register-transfer description to a manufacturable layout, explain what an on-chip bus provides and why one is used, and describe what integrating a purchased block actually involves.
Before:S4-4. Digital System DesignPE2-1. CMOS Analog and Digital IC DesignUnlocks:EC-25. Semiconductor Test, Packaging and Reliability
Almost no modern chip is designed from nothing. A system on a chip is a processor, some memory, a set of purchased interface blocks and a small amount of logic that is genuinely yours, connected by a standard bus so that the pieces fit together at all. This topic is the flow that produces such a thing and the practical business of integration, which is where most of the schedule actually goes.
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The flow from register-transfer source to a manufacturable layout
Synthesis, floorplanning, placement, clock tree construction, routing and physical verification each transform the design and each can fail. Naming the steps in order makes an unfamiliar tool chain navigable.
NPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi) · CourseHow a fixed-array device differs from a custom chip, and what each costs
One is configured in seconds for the price of the part, the other takes months and a large fixed cost and is then far cheaper and faster per unit. The crossover volume is the number that decides which a product uses.
NPTEL: Digital System Design with PLDs and FPGAs (IISc Bangalore) · CourseThe clock tree, and why building it is a step of its own
Delivering the same clock edge to a million registers at nearly the same instant needs a deliberately constructed network of buffers. The skew it achieves is what the hold analysis of the earlier topic depends on.
NPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee) · CourseOn-chip buses and interconnect: addresses, transfers and arbitration
A standard interconnect lets blocks from different sources be connected without each pair agreeing a private protocol. Understanding one such standard makes every other one legible.
NPTEL: System Design through Verilog (IIT Guwahati) · CourseIntegrating purchased blocks: what arrives, and what still has to be done
A purchased block comes with a description, constraints, a model and documentation, and integrating it still means resolving clocks, resets, address space and verification. The work is real even though the design is not yours.
Sign-off: the checks that must pass before anything is manufactured
Design rule checking, layout against schematic comparison, power analysis and final timing are the gates before a mask set is ordered. A mistake past this point costs months and a very large sum, which is why the checks are formal.
NPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi) · Course
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- FreeNPTEL / IIIT Delhi · CourseNPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi)
- FreeNPTEL / IISc Bangalore · CourseNPTEL: Digital System Design with PLDs and FPGAs (IISc Bangalore)
- FreeNPTEL / IIT Roorkee · CourseNPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee)
- FreeNPTEL / IIT Guwahati · CourseNPTEL: System Design through Verilog (IIT Guwahati)
Links last checked 4 Sept 2026.
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