EC-21.4 Timing: Constraints, Static Analysis and Closure

Work through these

• Setup and hold, from the flip-flop outward

  Setup asks whether the data arrived early enough before the clock edge and hold asks whether it stayed long enough after it. Every timing failure in a synchronous design is one of those two, on one specific path.

  NPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee) · Course

• Why static analysis, and what it checks that simulation cannot

  The analyser examines every path in the design against the clock definition rather than the paths one test happened to exercise. That exhaustiveness is why it finds problems a year of simulation would not.

  NPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee) · Course

• Writing constraints: clocks, input and output delays, false and multi-cycle paths

  The tool knows nothing about your intentions until the constraint file tells it, and an unconstrained path is not checked at all. Most timing surprises are missing constraints rather than slow logic.

  NPTEL: VLSI Design Flow — RTL to GDS (IIIT Delhi) · Course

• Reading a timing report: slack, the critical path and where the time went

  The report breaks a failing path into its stages so you can see whether the time went into logic, into wiring or into the clock arriving unevenly. Each of those three has a different remedy.

  NPTEL: VLSI Physical Design with Timing Analysis (IIT Roorkee) · Course

• Fixing a setup failure: pipelining, restructuring and retiming

  Setup failures are cured by shortening the logic between registers, either by adding a stage or by rearranging what is there. Adding a stage changes the latency of the design, which is a specification change and has to be agreed.

• Hold failures, clock skew, and why they are different in kind

  A hold failure cannot be fixed by slowing the clock down, which makes it far more alarming than a setup failure. It is usually a clock distribution problem rather than a logic one, and the tool inserts delay to fix it.