EC-21.7 From FPGA to ASIC: The Flow, the Buses, and Somebody Else's IP

What this is and why it exists

Almost no modern chip is designed from nothing.

A system on a chip is a processor, some memory and a set of purchased interface blocks. Beside them sits a modest amount of logic that is genuinely yours. The pieces are connected by a standard bus so that they fit together at all.

This topic is the flow that produces such a thing, and the practical business of integration. The second is where most of the schedule actually goes, and it is the part textbooks tend to omit.

The vocabulary

• Register-transfer source — the description a designer writes, before any physical form.
• Floorplanning — deciding where the large blocks sit on the die.
• Clock tree — the buffer network delivering the clock to every register.
• Layout — the final geometric description sent for manufacture.
• Non-recurring cost — the fixed cost of masks and setup, paid once.
• Interconnect standard — an agreed protocol for connecting blocks on a chip.
• Arbitration — deciding which of several requesters gets the bus.
• Purchased block — a design licensed from elsewhere and integrated into yours.
• Sign-off — the formal checks that must pass before manufacture.

The mental model

The flow is a sequence of transformations, each of which can fail. Synthesis turns source into gates. Floorplanning places the large blocks. Placement positions the individual cells. The clock tree is built. Routing connects everything. Physical verification checks the result. Naming the steps in order makes an unfamiliar tool chain navigable.

The choice between a fixed-array device and a custom chip is economic. One is configured in seconds for the price of the part. The other takes months, costs a large fixed sum, and is then far cheaper and faster per unit. The crossover volume is the number that decides which a product uses.

The clock tree deserves its own step. Delivering the same edge to a million registers at nearly the same instant requires a deliberately constructed network of buffers. The skew it achieves is exactly what the hold analysis of the timing topic depends on. That is why the two steps are adjacent in the flow.

An interconnect standard is what makes assembly possible. Without one, every pair of blocks would need a private agreement about addresses, transfers and who goes first. With one, blocks from four sources connect without negotiation. Understanding one such standard makes every other one legible.

Integrating a purchased block is real work even though the design is not yours. What arrives is a description, a set of constraints, a simulation model and documentation. What remains is resolving clocks, resets, address space and verification. Teams routinely underestimate this, and it is where schedules slip.

Sign-off is the set of gates before a mask set is ordered: design rule checking, layout compared against schematic, power analysis, and final timing. A mistake past this point costs months and a very large sum, which is why these checks are formal rather than a matter of judgement.

What you should now be able to explain or do

• List the steps from register-transfer source to a manufacturable layout, in order.
• Explain the economic choice between a configurable device and a custom chip.
• Say why clock tree construction is a step of its own, and what depends on it.
• Describe what an on-chip interconnect standard provides.
• List what arrives with a purchased block and what still has to be done.
• Name the sign-off checks and say why they are formal.

Check yourself