EC-21.6 Design for Test: Scan, Built-In Self-Test and Fault Coverage

What this is and why it exists

A finished chip has a few hundred pins and many millions of internal nodes.

No sequence of ordinary inputs will exercise them all in an acceptable time, and many internal results never reach a pin at all. So a manufactured part cannot be tested through its functional interface, and something has to be added to the design to make testing possible.

That something costs area and a little speed, and essentially every digital chip pays it. This is the designer's half of testing. What the factory then does with it is the subject of the semiconductor test module.

The vocabulary

• Controllability — how easily a node can be set to a chosen value.
• Observability — how easily its value can be seen at a pin.
• Stuck-at fault — a modelled defect holding a node permanently high or low.
• Fault coverage — the fraction of modelled faults the test patterns detect.
• Scan chain — registers connected into a shift register for test purposes.
• Test pattern generation — computing the inputs that expose each fault.
• Built-in self-test — on-chip logic that generates and checks its own patterns.
• Boundary scan — a standard interface for driving and observing chip pins.

The mental model

The problem is stated by two words. Controllability is how hard it is to put a chosen value on an internal node. Observability is how hard it is to see the result. Deep inside a state machine both can be effectively impossible through the functional inputs.

Scan solves both at once. A multiplexer is added to every flip-flop, so that in test mode all the flip-flops form one long shift register. The tester shifts in a state, runs one functional cycle, and shifts the result out. Every register becomes directly writable and directly readable.

The defect model is deliberately crude. A stuck-at fault treats every possible physical defect as a node held permanently at one level. That is plainly not what really happens. It works anyway, and the justification is empirical rather than theoretical: patterns that catch stuck-at faults catch most real manufacturing defects too.

Pattern generation is automatic. A tool computes, for each modelled fault, the inputs that make the fault visible at an observable point, and reports what fraction it could reach. A coverage figure below target points at logic no pattern can exercise, which is a design problem rather than a tool problem.

Built-in self-test takes a different route. Instead of shifting patterns in from outside, a small generator and checker on the chip test a block at full speed. Memories are almost always tested this way, because their regular structure makes the generator simple and the expected result cheap to compute.

Boundary scan extends the idea to the board. A standard four-wire interface lets a tester drive and observe every pin of every chip on an assembled board. That finds unsoldered joints and shorts. The same interface is also how many parts are programmed and debugged.

What you should now be able to explain or do

• Explain why functional inputs cannot test a large chip in reasonable time.
• Define controllability and observability, and say how scan improves both.
• Describe the stuck-at model and justify why such a crude model is used.
• Interpret a fault coverage figure and say what a low one indicates.
• Say why memories are tested by on-chip logic rather than by external patterns.
• Explain what boundary scan tests that chip-level test cannot.

Check yourself