PE2-1.4 Combinational CMOS Logic

What this is and why it exists

The digital half of this course starts from one circuit and one method, then asks what you would give up to go faster or smaller.

The inverter is the circuit. Complementary logic with a pull-up network and a pull-down network is the method. Everything else here is a departure from it, with a stated cost.

The vocabulary

• Static CMOS — complementary logic, where one network pulls the output up and a dual network pulls it down.
• Dual networks — two networks arranged so exactly one of them conducts for any input.
• Noise margin — how much disturbance an input can absorb before the output is wrong.
• Logic effort — a method of estimating delay from a gate's topology and sizing.
• Ratioed logic — logic whose output level depends on the ratio of two device strengths.
• Pass transistor logic — logic built from transistors used as switches.
• Threshold drop — the voltage lost when a single device passes a level it conducts poorly.
• Dynamic logic — logic that precharges a node, then conditionally discharges it.
• Charge sharing — a precharged node losing voltage to internal capacitances during evaluation.
• Transmission gate — an NMOS and a PMOS in parallel, passing both levels fully.

The mental model

Start with the inverter and read its transfer curve. It is flat near each rail and steep in the middle, and everything digital depends on that shape. The flat parts mean a small disturbance at the input produces almost none at the output. That is what lets logic be chained without noise accumulating. The noise margins and the switching threshold are read straight off that curve.

Static complementary design generalises it. Build a pull-down network from devices that conduct when their inputs are high. Then build a pull-up network that is its dual, conducting exactly when the pull-down does not. Series in one becomes parallel in the other. Once you see the duality, any complex gate follows from its expression without a truth table.

Static logic has two properties worth valuing. In a settled state no current flows from one rail to the other, so static power is near zero. And the output is actively driven to a full rail either way, so levels never degrade.

Logic effort is the tool that makes sizing systematic rather than guesswork. It separates a gate's delay into three parts. One depends on its topology, one on the load it drives relative to its own size, and one on its own internal capacitance. With those three you can estimate the delay of a whole path, and size each stage for minimum total delay, before running a single simulation.

Now the departures.

Ratioed logic replaces the complementary pull-up with a single always-on device. Fewer transistors and less area. The low output level is now set by the ratio of the two device strengths, rather than being a solid zero. It also burns current whenever the output is low. It was standard before complementary logic won and it survives where its area saving matters.

Pass transistor logic uses transistors as switches, passing an input through to the output. It can be very compact. Its problem is the levels. A single NMOS device passes a low level perfectly and a high level badly, losing roughly a threshold voltage. The degraded high level then makes the next stage leak, so a restoring stage is usually needed.

The transmission gate fixes exactly that, by putting an NMOS and a PMOS in parallel. Whichever level one passes poorly, the other passes well, so the full level gets through. That is why the pairing exists, and it appears inside the latches in the next topic.

Dynamic logic is faster and smaller. A clock precharges the output node high, then the pull-down network conditionally discharges it. Only one network is needed, so gates are smaller and their input capacitance is lower.

The value is held on a capacitance rather than driven, and that creates problems static logic does not have. Charge leaks away, so the node cannot be left indefinitely, which sets a minimum clock frequency. Internal capacitances inside the pull-down network can steal charge from the output during evaluation, which is charge sharing and can corrupt the level. And the inputs must be stable during evaluation, because there is no second chance once the node is discharged. Those timing rules are the price of the speed, and they are worth reading before deciding this option is straightforwardly better.

What you should now be able to explain or do

Read noise margins and switching threshold off an inverter transfer curve. Build any static gate from dual pull-up and pull-down networks. Use logic effort to size a path for minimum delay. Say what ratioed and pass transistor logic each save and each cost. Explain why a transmission gate needs both device types, and name the three problems dynamic logic introduces.

Check yourself