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PE2-1.4 Combinational CMOS Logic

You can design static CMOS logic and apply logic effort, and compare ratioed logic, pass transistor logic, dynamic logic and transmission gate logic on speed and power.

Logic effort is the tool that makes digital sizing systematic instead of guesswork — it predicts delay from topology and lets you size a path for minimum delay by hand. Dynamic logic is faster and smaller but it holds its state on a capacitance, so charge leakage, charge sharing and clock discipline all become your problem. Pass transistor logic saves transistors and loses a threshold voltage on the way through, which is exactly why the CMOS transmission gate pairs an NMOS with a PMOS.

Work through these

  • The static CMOS inverter

    The circuit the whole digital world is built from, and its transfer curve. Noise margins and the switching threshold read straight off that curve.

  • Static CMOS design

    The general method: a pull-up network and a pull-down network that are duals. Once you see the duality, any complex gate follows.

  • Logic effort and delay estimation

    A way to estimate delay before simulating, from the topology and the sizing. It makes digital sizing systematic instead of guesswork, which is why it earns its place.

  • Ratioed logic

    Logic where the output level depends on a device ratio, trading static power for area. It was standard before complementary logic won and it survives in specific places.

  • Pass transistor logic and its threshold drop

    Logic built from switches, which is compact and loses a threshold voltage on one edge. That loss is the reason it is usually combined with a restoring stage.

  • Dynamic logic

    Logic that precharges and then evaluates, which is faster and smaller. It also introduces timing rules that static logic does not have.

  • Speed and power dissipation in dynamic logic

    Where the speed comes from and what it costs in power, including the charge redistribution problems. Read this before deciding the previous item is straightforwardly better.

  • CMOS transmission gate logic

    The switch made from two complementary devices, which fixes the threshold loss above. It appears inside the latches in the next topic.

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Links last checked 30 Aug 2026.

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