PE2-1.5 Sequential CMOS Logic

What this is and why it exists

Combinational logic computes and forgets. A chip needs to remember, and this topic is how.

One structure dominates. The master-slave register is what almost every synchronous chip is clocked by. Its two-phase operation makes edge triggering possible from parts that are only level sensitive.

The vocabulary

• Latch — a storage element that is transparent while its control is active.
• Register — a storage element that captures its input on a clock edge.
• Cross-coupled inverters — two inverters output to input, the basic remembering structure.
• Transparent — passing the input straight to the output.
• Opaque — holding its stored value and ignoring the input.
• Master-slave — two latches in series on opposite clock phases.
• Edge triggered — capturing at the moment the clock changes, not while it is high or low.
• Setup time — how long the input must be stable before the clock edge.
• Hold time — how long it must stay stable after it.
• Dynamic latch — one holding its value on a capacitance rather than by feedback.

The mental model

Remembering, at bottom, is one idea. Connect two inverters in a ring. Whatever level is on the loop reinforces itself, so it stays. That cross-coupled pair is inside every static storage element in this topic.

A latch is that pair with a way in. While its control is active the latch is transparent and the input passes through. When the control goes inactive the loop closes and the value is held. It is one bit of memory, and it has one flaw for synchronous design. While it is transparent, changes at the input reach the output immediately.

The multiplexer-based latch is the compact way to build it. A selector chooses between the input and the stored value, so one control selects transparent or holding. Built from the transmission gate of the previous topic it costs few devices, and it is what most standard cell libraries actually contain.

The set-reset flip-flop is the ancestor. Two cross-coupled gates with two inputs, one to force a one and one to force a zero. Its famous flaw is that asserting both at once is meaningless, and what happens when they are released together is unpredictable. Worth knowing as the origin of everything else here.

Now the structure that matters. Put two latches in series and drive them on opposite clock phases. While the clock is low, the first is transparent and the second is holding, so the input reaches the middle and no further. When the clock rises, the first goes opaque and the second becomes transparent, so the value trapped in the middle moves to the output. At no moment is there a path straight through.

The consequence is edge triggering. The output changes once, on the clock edge, from the value captured immediately before it. Two level-sensitive parts have produced an edge-sensitive whole, and that is what every synchronous design is built from.

Setup and hold time fall out of that structure rather than being imposed on it. The input must arrive early enough for the first latch's loop to settle before it closes, which is setup time. It must stay long enough after the closing for the loop to hold, which is hold time. Understanding that origin turns timing analysis into reasoning rather than rule-following.

Dynamic storage is the same bargain as in the previous topic. Drop the feedback loop and hold the value as charge on a capacitance. Far fewer devices, and the charge leaks. So a dynamic register must be clocked at least as often as the leakage allows, which puts a lower limit on clock frequency. That is an unusual constraint, because almost everything else in digital design has an upper limit instead.

What you should now be able to explain or do

Explain why cross-coupled inverters remember. Build a latch from a multiplexer and say why libraries use that form. Say why a single latch cannot be used as a synchronous storage element. Explain how two latches on opposite phases give edge triggering. Derive setup and hold time from the latch structure, and say why a dynamic register has a minimum clock frequency.

Check yourself