OE-10.3 CMOS Logic Circuit Design

What this is and why it exists

The complementary inverter is this unit's centre of gravity, and one property of it explains why integration could scale at all.

A pull-up network and a pull-down network that are complements of one another. Whatever the input, exactly one of them conducts. So in a settled state there is no path from supply to ground, and the gate draws almost no static current.

That is why millions of gates can share one chip without melting it. Power is spent switching, not sitting.

The vocabulary

• Pull-down network — transistors connecting the output to ground.
• Pull-up network — transistors connecting the output to the supply.
• Complementary — the two networks conduct under opposite conditions.
• Static current — current drawn while nothing is changing.
• Transfer characteristic — output voltage plotted against input voltage.
• Noise margin — how much disturbance an input tolerates before the output is wrong.
• Dual network — the arrangement obtained by swapping series and parallel.
• Transmission gate — a pair of transistors used as a switch passing either level.

The mental model

Start with the older approach for contrast. An inverter built with a fixed load device conducts continuously in one of its states, so it burns power whenever it holds that value. Fine for a handful of gates; impossible for a million.

The complementary arrangement removes that. Two networks, conducting under opposite conditions, so one is always off. Static power falls essentially to leakage, and power becomes something spent during transitions rather than during rest.

The transfer characteristic is the next thing to read properly. Plot output against input and you get a curve that is flat, then falls steeply, then flat again. The flat regions are where the gate is confident, and the steep region is where it is deciding. The width of the flat regions is the noise margin — how much an input can be disturbed before the output changes. A gate with poor margins works on a bench and fails in a system.

Now the design rule that makes every gate in this family constructible. Build the pull-down network so that it conducts exactly when the output should be low: series for AND-like conditions, parallel for OR-like ones. Then make the pull-up network its dual, swapping series for parallel throughout. That gives you NAND, NOR, and the compound gates directly.

The compound gates are worth a moment. Once you see a Boolean function as a pull-down network and its dual, an and-or-invert gate stops being a memorised structure. It becomes something you derive. That is the intended payoff of this topic.

The transmission gate is the different idea here. It is a switch that passes a signal rather than driving one, using both transistor types together. Either type alone passes one logic level well and the other badly. Two together pass both. Flip-flops built this way are compact, and it is worth noticing that this is a genuinely different style from the network approach above.

What you should now be able to explain or do

Say why the complementary arrangement draws almost no static current, and why that permitted scale. Read a transfer characteristic and identify the noise margin. Build a pull-down network for a Boolean condition. Derive the pull-up network as its dual. Construct compound gates by that method rather than by memory. Say why a transmission gate needs both transistor types.

Check yourself