OE-10.4 Memory Cell Design

What this is and why it exists

This unit contains one of the cleanest cost-against-speed trades in all of engineering, and it is worth studying as an example of trade-offs generally.

One transistor and a capacitor is dense, cheap per bit, and forgets — it must be refreshed constantly. Six transistors are fast and stable and expensive in area.

That is the whole reason your computer has a small amount of very fast memory and a large amount of slower memory. The trade is not a compromise somebody settled for; it is a choice made twice, on purpose, in the same machine.

The vocabulary

• Dynamic storage — a value held as charge, which leaks away.
• Static storage — a value held by a circuit that actively maintains it.
• Refresh — reading and rewriting a dynamic cell before it forgets.
• Destructive read — reading the cell destroys the stored value.
• Sense amplifier — a circuit detecting a very small voltage difference.
• Cell area — the silicon one bit of storage occupies.
• Read-only memory — contents fixed when manufactured.

The mental model

A dynamic cell stores a bit as charge on a capacitor, with one transistor as the switch that lets you at it. That is as small as storage gets. The cost is that the charge leaks, so every cell must be read and rewritten periodically or the data is lost. Refresh is not a maintenance chore, it is a permanent tax — it consumes bandwidth and power for as long as the machine is on.

The read is destructive, too. Getting the charge out removes it, so every read is followed by a write-back. And the charge is tiny, which is why sense amplifiers exist. They decide a bit from a voltage difference far too small to use directly. The three-transistor version is a stepping stone showing the idea with a non-destructive read. The one-transistor version is what is manufactured, because density wins.

A static cell is a pair of inverters looped so each holds the other's input, plus two access transistors. It maintains itself and needs no refresh, so it is fast and its behaviour is simple. It costs six transistors per bit, several times the area. That area is exactly why it is used for caches and not for main memory.

So the two are not competitors. They occupy different points on one trade, and a machine uses both. Static memory close to the processor where speed decides, dynamic memory further out where capacity decides.

Read-only structures differ in a similar way. A parallel arrangement of transistors is fast and takes more area. A series arrangement is dense and slower, because a read must pass through a chain rather than a single device. Same shape of trade, third instance in one unit, which is the point worth carrying away.

What you should now be able to explain or do

Describe the one-transistor dynamic cell and the six-transistor static cell. Say what refresh costs continuously, not merely that it is needed. Explain the destructive read and why sense amplifiers are required. Say why static memory is used for caches and dynamic for main memory. Compare the two read-only structures on the same axis. Recognise the trade recurring three times in this unit.

Check yourself