EC-25.1 Variability, Yield, and What a Process Actually Delivers
The standard opening treatment of process variability and yield: systematic and random variation, corner and statistical simulation, defect density, redundancy and binning, September 2026
What this is and why it exists
Two transistors drawn identically and made on the same wafer are not identical.
Everything in semiconductor manufacturing follows from that. Some of the difference is systematic and can be modelled and compensated. Some is atomic, and cannot be.
Yield is the fraction of manufactured parts worth selling, and for most products it is the number the business runs on. That is why a design change improving yield beats one improving speed, and why a designer who ignores yield is expensive to employ.
The vocabulary
- Variability — the spread in a parameter across devices that should be identical.
- Systematic variation — a difference that follows a pattern, such as a gradient.
- Random variation — a difference with no pattern, down to atomic statistics.
- Process corner — a combination of extreme parameter values used in simulation.
- Monte Carlo — simulation using randomly drawn parameter sets.
- Defect density — the number of killing defects per unit area of wafer.
- Yield — the fraction of dies that work well enough to sell.
- Redundancy — spare circuits that can replace defective ones after test.
- Binning — sorting parts by measured performance and selling them separately.
The mental model
Variation has sources you can name. Lithography does not print exactly the drawn shape. Implantation places a distribution of dopant atoms rather than a fixed number. Deposition and etching vary across a wafer and between wafers. At small dimensions the number of dopant atoms in a channel is small enough that ordinary counting statistics matter.
The distinction that changes decisions is systematic against random. A gradient across a wafer affects neighbouring devices almost equally, so a matched pair placed close together cancels it. An atomic-scale fluctuation between two adjacent devices does not cancel, and no layout technique removes it. This is precisely why analog designers place matched devices together and in a common orientation.
Two kinds of simulation answer two different questions. Corner simulation asks whether the design survives the extremes. Monte Carlo asks how many parts fall outside the specification. A design can pass every corner and still lose a tenth of production, because corners are not a distribution.
Yield follows from defect density and die area. Given a defect density, the probability of a die being free of killing defects falls quickly as area grows. That is why large chips cost far more than their size suggests, and it is a calculation worth doing once by hand.
Redundancy is the direct response. Spare rows and columns in a memory, substituted after test, turn many defective dies into sellable ones. It is the clearest example of a design decision made purely to raise yield.
Finally, binning. Parts failing the fastest specification often pass a slower one, and are sold as a different product. That is why a product family can share one design and one mask set, and why the fast parts cost so much more.
What you should now be able to explain or do
- Name the process steps that contribute variation, and what each contributes.
- Explain why systematic variation can be designed around and random cannot.
- Say what corner simulation and statistical simulation each answer.
- Relate defect density and die area to yield.
- Explain how memory redundancy converts defective dies into sellable ones.
- Say why one design and one mask set produce several products.
Check yourself
Why are matched analog devices placed close together?
Because systematic variation is smooth across a wafer. Neighbouring devices see almost the same value, so the difference between them nearly cancels.
A design passes all process corners but a tenth of production fails. How?
Corners are not a distribution. Statistical simulation asks how many parts fall outside the specification, which corner analysis cannot answer.
Why does a chip twice the area cost far more than twice as much?
Because yield falls quickly with area. A larger die is more likely to contain a killing defect, so fewer of them survive per wafer.
What is binning?
Sorting finished parts by measured performance and selling them as different products. The same design and mask set then serve a whole product family.
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