EC-25.3 Testing a Wafer, and Testing a Package

What this is and why it exists

The verification module put scan chains into the design. This is what the factory does with them.

Every die is tested before the wafer is cut, because packaging a dead die wastes the package. Every packaged part is tested again, because packaging breaks things.

Test is a large fraction of the cost of a chip. So almost every decision here is about buying the most confidence per second of tester time. That constraint shapes what the design has to provide.

The vocabulary

• Wafer sort — testing every die while still on the wafer.
• Probe card — the fixture that contacts a die's pads on the tester.
• Automatic test equipment — the machine that applies patterns and measures responses.
• At-speed test — running the part at its rated speed to catch delay faults.
• Test compression — on-chip logic letting few pins deliver many patterns.
• Final test — testing the packaged part.
• Escape — a bad part that passes the test.
• Overkill — a good part rejected by the test.
• Guard band — margin added to a limit to account for measurement uncertainty.
• Known good die — a die proved before being assembled with others.

The mental model

Wafer sort comes first, and its logic is economic. A package costs money and assembly time, so testing before packaging avoids spending both on a dead die. The map of which dies passed is also the first yield data anybody sees, and its pattern often points at the process step responsible.

The tester applies patterns through the scan interface and compares responses against what the design should produce. It can also run the part at its rated speed to catch faults that only appear as delay rather than as a wrong value. That second kind of test costs far more machine time, which is why it is applied selectively.

Test time is a cost that appears in the price of the part. Scan patterns are long, and a tester has a limited number of pins. Compression logic on the chip expands a few tester channels into many internal scan chains, delivering the same coverage in a fraction of the time. It is a design feature that exists purely for the factory.

Final test repeats much of this on the packaged part. Bonding, moulding and handling all introduce their own failures, so a die that passed at sort can fail afterwards. Final test also measures parameters that only exist once the package is on, such as timing through the package inductance.

Setting a limit is where engineering meets commerce. A limit tight enough to catch every bad part rejects good ones as well. Measurement uncertainty has to be added as a guard band on top of that. Where the limit sits is decided by what a field failure costs, which makes it a business decision informed by engineering.

Finally, known good die. When several dies are packaged together, one bad die scraps the whole assembly. Each must therefore be proved before assembly, which is what makes advanced packaging a test problem as much as a mechanical one.

What you should now be able to explain or do

• Say why wafer sort exists and what its output map tells you.
• Describe what a tester does with a scan interface.
• Explain why at-speed test is applied selectively.
• Say what test compression buys and why it is a design feature.
• Explain why a packaged part is tested again after sort.
• Set a test limit accounting for uncertainty, escapes and overkill.

Check yourself