EC-24.4 Stack-Up, Placement and Routing

What this is and why it exists

Layout looks like a puzzle. It is really a sequence of decisions made in the right order.

The stack-up comes first, because it decides what impedances and what routing density are available. Placement comes second, and determines perhaps eighty per cent of the outcome. Routing is last.

If routing is difficult, the answer is almost always to go back and move something. Fighting a hard route is the commonest way to waste a week on a board.

The vocabulary

• Stack-up — the arrangement of copper and insulating layers through the board.
• Reference plane — a solid copper layer adjacent to a signal layer.
• Dielectric — the insulating material between copper layers.
• Placement — deciding where each component sits.
• Copper weight — the thickness of the copper, which sets current capacity.
• Via — a plated hole connecting layers.
• Annular ring — the copper around a drilled hole, which must not break out.
• Capability table — the fabricator's published limits on widths and spacings.
• Output files — the layer and drill data actually sent for manufacture.

The mental model

Every signal layer wants an adjacent reference plane, and the spacing to it sets both the impedance and the loop area. That is the reason a four-layer board is so much better behaved than a two-layer one. Adding two layers is usually cheaper than a redesign caused by not having them.

Placement is where the board is really designed. Connectors are fixed by the enclosure. Hot parts need somewhere to dissipate. Sensitive parts must be away from noisy ones. Related parts belong together so the traces between them are short. A layout that is hard to route is nearly always a placement decided too quickly.

Trace width follows from current and the acceptable temperature rise. The standard charts are conservative, and they are also what a reviewer will check against, so using them is the path of least argument. Copper weight enters here too, since thicker copper carries more current in the same width.

Vias cost money as well as space. Through-holes are cheap, while blind and buried vias raise the price sharply. A design needing the expensive kind should need it for a stated reason. Vias also add inductance, which matters in a supply path and in a high-speed signal.

Every fabricator publishes a capability table: minimum trace width, minimum spacing, smallest drill, smallest annular ring. Prices rise steeply outside the standard column. Designing to that column is the single cheapest decision available on most boards.

Finally, the manufacturer builds from the exported layer and drill files, not from your design file. An export mistake is invisible inside the tool. Opening the outputs in a separate viewer takes five minutes and prevents a scrapped batch.

What you should now be able to explain or do

• Choose a stack-up and justify each layer's purpose.
• Place components in the order the constraints demand.
• Size a trace from its current and an acceptable temperature rise.
• Choose a via type and say what it costs to manufacture.
• Design to a fabricator's standard capability column.
• Check exported manufacturing files in an independent viewer.

Check yourself