EC-24.5 Signal Integrity and Power Integrity

What this is and why it exists

The electromagnetics module gave you the transmission line. This is what it means for a board.

The threshold is not the clock frequency. It is the edge rate. A slow signal with a sharp edge on a long trace will ring, and a great many designers have been caught by exactly that.

Power integrity is the same physics applied to the supply. The impedance a chip sees looking back into its power network has to stay low across a very wide frequency range. Keeping it there is a design activity, not an assumption.

The vocabulary

• Edge rate — how fast a signal transitions between levels.
• Electrical length — the propagation delay along a trace, compared to the edge rate.
• Termination — a component arrangement that absorbs reflections.
• Crosstalk — a signal coupled from one trace into a neighbouring one.
• Near end and far end — the two places coupled energy appears.
• Skew — the difference in arrival time between signals that should be simultaneous.
• Differential pair — two traces carrying equal and opposite signals.
• Power distribution impedance — what a chip sees looking into its supply.
• Eye diagram — many symbol periods overlaid, showing remaining margin.

The mental model

A trace behaves as a transmission line when the round-trip delay along it is comparable to the signal's rise time. Notice what is absent from that statement: the clock frequency. A ten-kilohertz signal with a one-nanosecond edge on a long trace rings exactly as a fast clock would.

When it does, a mismatch at either end sends energy back. Termination absorbs it. A series resistor at the driver, a parallel resistor at the receiver, a split arrangement or an alternating-current termination are the four common answers. Which suits depends on the driver's strength, the topology and how much static power you can spend.

Crosstalk comes from two traces running close and parallel. They couple through both capacitance and inductance, and the coupled voltage grows with the length they run together. Energy appears at both ends of the victim trace, with different polarity and timing. The usual remedy is separation measured in trace heights above the plane rather than in millimetres.

Length matching solves the timing half. A parallel bus needs its bits to arrive together, and a differential pair needs its two halves to stay in step. Both are met by matching physical length, which is why serpentine wiggles appear on fast boards. They are not decoration.

Power integrity is the same problem on the supply. A chip demands current at frequencies from constant to gigahertz, and the network has to look low impedance across all of it. Different capacitor sizes cover different bands, and the resonances between them can leave gaps that are worse than either capacitor alone.

Finally, the eye diagram is the evidence. Overlay many symbol periods and look at how much room remains in amplitude and in time. A closing eye says the margin is going, before anything actually fails.

What you should now be able to explain or do

• Decide whether a trace must be treated as a transmission line, from the edge rate.
• Choose and place a termination, and say what it costs.
• Explain near-end and far-end crosstalk, and the spacing rule that controls both.
• Say why serpentine routing exists on a fast bus.
• Explain why a power network needs several capacitor sizes.
• Read an eye diagram as a statement about remaining margin.

Check yourself