S4-4.3 Sequential Logic Design

What this is and why it exists

Combinational logic has no yesterday: outputs follow inputs, full stop. Add memory and circuits acquire history — counters that know where they are, registers that hold what they were told, state machines that behave differently because of what happened before. This unit carries the two distinctions interviewers test first (latch versus flip-flop, blocking of time via setup and hold) and ends at the crown of undergraduate digital design: turning a word problem into a synchronous finite state machine.

The vocabulary

• Latch — level-sensitive storage: transparent while its enable is active, holding when it is not.
• Flip-flop — edge-triggered storage: samples its input only at the clock edge; opaque at every other instant.
• SR, D, T, JK — the flip-flop dialects: set-reset, data, toggle, and JK which removes SR's forbidden input combination.
• Master-slave JK — two latches in series so the output changes once per clock, curing the race-around problem.
• Setup and hold time — the window around the clock edge during which the data input must not change.
• Ripple vs synchronous counter — clocking each stage from the previous stage's output, versus clocking every stage together.
• Finite state machine (FSM) — states, transitions on inputs, and outputs; Moore outputs depend on state alone, Mealy outputs on state and input.
• ASM chart — the FSM drawn as a flowchart shaped for direct hardware implementation.

The mental model

A latch is an open door while enabled — whatever is at the input walks straight through, and changes keep walking through until the door shuts. A flip-flop is an airlock: once per clock edge it admits exactly what stood at the input at that instant, and nothing else gets in between edges. Nearly all modern design is airlocks on a common clock — synchronous design — because when every element samples at the same moment, time itself becomes discrete and reasoning becomes tractable.

Setup and hold are where digital design admits its analog foundations. The input must be steady for a small window before the edge (setup) and after it (hold), because the sampling circuit needs that long to commit cleanly. Violate the window and the output may hover between logic levels before falling either way — metastability. The deadly phrase is "works, usually": a timing-marginal circuit passes the demo and fails in the field, which is worse than never working, and it is why timing analysis is a signoff step, not a courtesy.

Counters make the ripple-versus-synchronous trade concrete. A ripple counter clocks each stage from its neighbour — minimal wiring, but the edges arrive later and later down the chain, and mid-transition the count reads garbage. A synchronous counter clocks all stages together and spends gates computing which should toggle: clean, fast, standard. Shift registers reuse the same airlocks to move data sideways — serial-parallel conversion in both directions.

FSM design is the unit's summit and it is a recipe: name the states a word problem implies, draw the transitions, choose Moore or Mealy (Moore's outputs are steadier; Mealy often needs a state fewer and reacts a cycle sooner), assign state codes, derive next-state and output logic through K-maps, and build. A sequence detector — three specific bits in a row lights an output — is the classic first run. ASM charts are the same machine drawn as boxes and decision diamonds, one clock per column, which is the form implementation-minded engineers prefer.

What you should now be able to explain or do

Give the latch-versus-flip-flop distinction in two sentences. Convert between D, T and JK flip-flops. Explain setup, hold and metastability and why "usually works" is a defect. Design a synchronous counter and a small FSM from words to gates, and verify each in simulation.

Check yourself