S4-4.3 Sequential Logic Design

Work through these

• Latches vs flip-flops; level vs edge triggering

  A latch responds whenever its enable is high; a flip-flop responds only at a clock edge. This is the first thing an interviewer probes and the source of most beginner bugs in sequential design.

• SR, D, T, JK and Master-Slave JK flip-flops

  The standard one-bit memory elements, each with its own behaviour table, and the master-slave arrangement that made edge triggering possible before dedicated edge circuits existed. D and JK are the two you will actually use.

• Flip-flop conversions

  Any flip-flop can be made to behave as any other by adding a little logic at its inputs, and the conversion procedure is a standard examination exercise. It also demonstrates that the differences between them are conventions rather than physics.

• Setup and hold times

  Data has to be steady for a moment before the clock edge and for a moment after it, or the flip-flop stores something undefined. This is where digital design admits it stands on analog reality, and violating these times gives a circuit that works usually, which is worse than never.

• Ripple and synchronous counters; shift registers

  Counters count clock pulses and shift registers move data along one position per clock. The ripple against synchronous distinction repeats the timing lesson: letting stages clock each other is cheap and accumulates delay.

• Finite state machines: design of a synchronous FSM

  A finite state machine turns a word problem into a set of states and the transitions between them, and it is the crown of this unit. Once you can do that translation, almost any control logic becomes designable.

• Algorithmic State Machine charts

  An algorithmic state machine chart is a state machine drawn in a form that maps directly onto an implementation. It is the notation that carries a design from idea to hardware.

• Lab: design, simulate and verify a synchronous counter and a small FSM

  Design, simulate and verify a synchronous counter and a small state machine. This is the item that proves the unit landed, because a state machine that misbehaves shows exactly which transition was wrong.