core Estimated learning time: 8 h

PE2-1.5 Sequential CMOS Logic

You can design static latches and registers, MUX-based latches, static SR flip-flops and master-slave edge triggered registers, and describe dynamic latches and registers.

The master-slave register is the structure almost every synchronous chip is clocked by, and its two-phase operation is what makes edge triggering possible from level-sensitive parts. Static versus dynamic is the same bargain as in the previous unit: static holds its value indefinitely at the cost of transistors, dynamic is small and must be refreshed before the charge leaks away. Setup and hold time appear here as consequences of the internal structure rather than as datasheet numbers.

Work through these

  • Static latches and registers

    The circuits that remember, which is where combinational design becomes sequential. Cross-coupled inverters are the underlying idea in every one of them.

  • MUX based latches

    Building a latch from the switch structure at the end of the previous topic. It is compact and it is what most standard cell libraries actually contain.

  • Static SR flip-flops

    The classic storage element and its forbidden input combination. Worth knowing as the ancestor of everything else here.

  • Master-slave edge triggered register

    Two latches in series so the output changes only on an edge. It is the flip-flop every synchronous design is built from.

  • Dynamic latches and registers

    The storage that relies on charge rather than feedback, which is smaller and leaks. It sets a minimum clock frequency, which is an unusual constraint.

  • Setup and hold time as consequences of latch structure

    Where timing requirements come from: they fall out of the latch structure rather than being imposed. Understanding that makes timing analysis reasoning rather than rule-following.

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Links last checked 30 Aug 2026.

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