OE-10.4 Memory Cell Design
You can design dynamic register elements, 3T and 1T DRAM cells and the 6T SRAM cell, and lay out NOR- and NAND-based ROM.
The 1T DRAM cell against the 6T SRAM cell is one of the cleanest cost-versus-speed trades in all of engineering: one transistor and a capacitor is dense but forgets and must be refreshed, six transistors are fast and stable but expensive in area. NOR and NAND ROM structures differ in speed and density the same way, and the NAND arrangement is the ancestor of flash memory. Count transistors per bit as you go; that number is the whole argument.
Work through these
Design of a dynamic register element
Storage that relies on charge held on a capacitance, which is where the dynamic family starts. The charge leaks, which is why refresh exists.
3T dynamic RAM cell
The three-transistor cell, which reads without destroying what it stored. Larger than the next one and simpler to use.
1T dynamic RAM cell
The one-transistor cell, which is what makes large memory economic. Reading destroys the contents, so the sense amplifier and the write-back are part of the design.
6T static RAM cell
The static cell, which holds its value without refresh at the cost of area. The comparison with the two cells above is the content of this topic.
NOR-based ROM memory design
Read-only storage built as a wired arrangement of devices, in the faster and larger form. The comparison with the next item is a familiar speed against density trade.
NAND-based ROM memory design
The same function built the other way: slower, denser, and what large read-only arrays actually use.
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