S5-4.4 Logic Families
Standard linear and digital integrated-circuit theory, and the published behaviour of the parts named — written September 2026
What this is and why it exists
A logic family is not a set of gates. It is a set of promises about voltages, currents and timing.
Two chips from the same family can be wired together safely because they make the same promises. Two chips from different families can only be wired together after you check that the promises line up. That check is what this topic is for.
The vocabulary
- Fan-out — how many inputs one output can drive and still meet its voltage promises.
- Noise margin — the voltage of interference an input can absorb before it reads the wrong level.
- Propagation delay — the time from an input change to the matching output change.
- Power dissipation — the power a gate consumes, both while idle and while switching.
- TTL — transistor-transistor logic, the older bipolar family.
- Totem pole — a TTL output that actively drives both high and low.
- Open collector — an output that can only pull low, needing an external pull-up resistor.
- Tri-state — an output that can also be turned off entirely, releasing the wire.
- CMOS — complementary metal-oxide-semiconductor logic.
- Transmission gate — a switch made from two complementary transistors in parallel.
- Open drain — the CMOS equivalent of an open collector output.
The mental model
Four numbers specify a family, and each has a plain meaning.
Fan-out is a current question. An output can source and sink only so much, and each input it drives takes a share. Exceed the fan-out and the voltage levels no longer meet the promise. Noise margin is the gap between the worst voltage an output guarantees and the worst voltage an input accepts. It is the interference the wire may pick up before something is misread. Propagation delay sets how fast the circuit can be clocked. Power dissipation sets how hot it gets and what the supply must provide.
Interfacing two families is exactly a matter of comparing these four, in both directions.
TTL's three output stages answer three different needs, and the differences matter.
A totem pole output has one transistor pulling up and another pulling down. It drives both directions actively, so it is fast. It also means two such outputs must never be joined, because one pulling up against another pulling down is a short across the supply.
An open collector output can only pull down. A resistor to the supply does the pulling up. That looks like a downgrade and it buys two things. Several open collector outputs can share one wire. The wire goes high only when every one of them releases it, which gives a logical AND for free. The pull-up resistor may also go to a different supply voltage, which shifts levels between families.
A tri-state output is a totem pole with a third condition: both transistors off, so the output is disconnected. Many drivers can then share one wire as long as only one is enabled at a time. That is how every bus in every computer works, so it is the one to be sure of.
CMOS is the family that won, and its reason is simple. A CMOS gate has complementary transistors arranged so that, once settled, one of them is always off. Almost no current flows between the rails while the state is steady. Static power is therefore near zero, and power is consumed mainly while switching. That is the same property that made large scale integration possible, so this fact runs well beyond the topic.
The transmission gate is a genuinely useful building block: two complementary transistors in parallel, acting as a switch that passes a signal in either direction. It appears inside multiplexers and latches, so recognising it pays off later. Open drain and high impedance outputs are the CMOS equivalents of open collector and tri-state, and comparing the pairs is quicker than learning them twice.
The comparison the topic builds towards is three trades, not a winner. TTL is generally faster in its older forms and consumes power constantly. CMOS consumes almost nothing when idle, and its consumption rises with clock frequency. CMOS has the wider noise margin, because its thresholds sit near the middle of a wider supply range.
What you should now be able to explain or do
Define fan-out, noise margin, propagation delay and power dissipation, and use them to check an interface. Say why two totem pole outputs must not be joined and why two open collector outputs may be. Explain what tri-state adds and why buses depend on it. Say why CMOS static power is near zero and why its power rises with frequency. Compare the two families as three trades rather than a ranking.
Check yourself
What does noise margin actually measure?
The gap between the worst voltage an output guarantees and the worst an input will accept. It is the interference a wire may pick up safely.
Why must two totem pole outputs never share a wire?
If one drives high while the other drives low, current flows straight from the supply to ground through both. That is a short circuit.
What do you get by joining several open collector outputs?
A wire that goes high only when every output releases it. That is a logical AND made from wiring, with one pull-up resistor.
Why is CMOS static power near zero?
In a settled state one of the complementary transistors is always off, so there is no path from one supply rail to the other.
Why does CMOS power consumption rise with clock frequency?
Power is spent charging and discharging capacitance at each transition. More transitions per second means more of that charging.
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