S5-4.5 Combinational, Sequential Circuits & Memories

What this is and why it exists

An earlier digital course designed logic from gates and truth tables. This topic designs it from parts with order codes.

The shift matters. A ripple counter and a synchronous counter both count, and how they differ is written in their datasheets rather than in the theory. Reading the part is now half the work.

The vocabulary

• Decoder — a part that raises exactly one output for each input combination.
• Multiplexer — a part that selects one of several inputs onto a single output.
• Serial adder — an adder that handles one bit position per clock.
• Parallel adder — an adder with hardware for every bit position at once.
• BCD adder — an adder that corrects its result to stay in decimal digits.
• Asynchronous counter — each stage is clocked by the previous one, so changes ripple along.
• Synchronous counter — every stage is clocked together from one clock.
• ROM and RAM — memory that is read only in normal use, and memory that is read and written.
• Word size and capacity — how wide each stored item is, and how many there are.
• PAL and PLA — programmable logic parts, configured rather than wired.
• CPLD and FPGA — larger programmable parts, holding whole designs.

The mental model

A decoder raises one output for each input combination, so its outputs are the minterms of its inputs. Any logic function is a sum of minterms, so an OR gate across the right decoder outputs implements any function you like. That is a change of perspective rather than a new device.

A multiplexer does the same job more usefully. Wire the variables to the select inputs and set each data input to the value the function should take for that combination. A part with three select inputs implements any function of three variables directly, and with one more trick it handles four. This is a genuinely handy skill.

The three adders trade speed against hardware, which is the axis running through this whole subject. A serial adder handles one bit position per clock, so it is small and slow. A parallel adder has hardware for every position, so it is large and fast. Its speed is limited by the carry rippling from one end to the other. The decimal adder exists because people want decimal answers. It adds in binary and then corrects any result that has left the range of a decimal digit.

The two counters are where the topic's shift becomes concrete. In the asynchronous part each stage clocks the next, so a change ripples along the chain. Every stage adds its own delay, and during that ripple the outputs briefly show values the counter never intended. In the synchronous part one clock reaches every stage at once, and extra logic decides which stages should change. It costs more logic and it settles in one gate delay. Comparing the two on the same task is what shows you why the extra logic is worth it.

Memory has a vocabulary worth settling before anything else. Read only memory keeps its contents without power and is written rarely or never. Read and write memory is fast and forgets when power is removed. Internally, a memory is an array of cells with a row decoder and a column selector. The timing numbers on the datasheet are the delays through that structure.

Expanding memory is the practical skill. Two chips side by side make each stored word wider. Two chips one after another make more words, with an address bit choosing between them. Almost every real design does one of these, or both.

The programmable parts invert the whole approach. Instead of wiring fixed parts together, you configure one part until it becomes the logic you wanted. A PLA has a programmable array of ANDs feeding a programmable array of ORs. A PAL fixes the second array, which is cheaper and covers most needs. Complex programmable devices and field programmable gate arrays carry that idea to whole designs, and they are the technology most students will actually use.

What you should now be able to explain or do

Implement an arbitrary logic function with a decoder and again with a multiplexer, and say which you would choose. Compare serial, parallel and decimal adders on speed and hardware. Explain why a ripple counter shows values it never intended, and what synchronous clocking buys. Expand a memory in width and in depth. Describe what a PAL, a PLA and an FPGA each let you configure.

Check yourself