S5-4.3 555 Timer, Voltage Regulators & Data Converters
Standard linear and digital integrated-circuit theory, and the published behaviour of the parts named — written September 2026
What this is and why it exists
This topic collects three families of catalogue part that turn up in almost every design. Something to make timing, something to make a clean supply, and something to cross between the analog and digital worlds.
None of them is deep. All of them are used constantly, and the comparisons between the converter types are the real content.
The vocabulary
- Monostable — one output pulse of a chosen length, produced when the circuit is triggered.
- Astable — free running oscillation with no trigger needed.
- Duty cycle — the fraction of each period the output spends high.
- Fixed regulator — a three terminal part giving one output voltage, such as the 7805 at five volts.
- Adjustable regulator — a part such as the 723, whose output you set with external components.
- Resolution — the number of distinct output steps a converter offers.
- Weighted resistor DAC — one resistor per bit, each a different precise value.
- R-2R ladder — a network using only two resistor values, repeated.
- Flash conversion — comparing the input against every level at once.
- Successive approximation — deciding the output one bit at a time, from the top down.
- Dual slope conversion — charging for a fixed time, then discharging at a fixed rate and timing it.
The mental model
The 555 is the most produced integrated circuit in history, and it is worth knowing from the inside. It contains two comparators, a flip flop, a discharge transistor and a chain of three equal resistors. That chain sets the comparators at one third and two thirds of the supply. Both operating modes fall out of those two thresholds.
In monostable mode an external capacitor charges through a resistor. The output stays high until the capacitor reaches two thirds of the supply, then the flip flop resets and the discharge transistor empties it. The pulse length is therefore set by that resistor and capacitor, and works out to about one point one times their product. Learn it well enough to design to a period rather than to look one up.
In astable mode the capacitor charges to two thirds and discharges to one third, over and over. Charging goes through both resistors and discharging goes through only one, so the high time is longer than the low time. That asymmetry is what sets the duty cycle, and it is the detail people miss. The time for each stage is the resistance times the capacitance times about zero point six nine, which is the natural logarithm of two.
Regulators come in two kinds. The fixed three terminal part is almost too convenient to think about: rough supply in, five volts out. The adjustable part is where you actually design, and it is the one that teaches what a regulator is doing. Inside it there is a voltage reference and a pass transistor. Between them sits an error amplifier, comparing a fraction of the output against that reference. It is a feedback loop, exactly like the circuits in the previous topic. Loading the output until it drops is the measurement that teaches the most.
Now the converters, and here the comparison is the content.
On the output side, the weighted resistor design uses one resistor per bit, each twice the previous. It is simple and it does not scale. An eight bit converter needs eight precise values spanning a range of two hundred and fifty six to one. The R-2R ladder gets the same result from only two values, repeated. That is a manufacturing argument rather than a circuit one. Making many precise ratios on one chip is hard, and making two is not.
On the input side there are three architectures and one trade. Flash conversion compares the input against every level at once, using a comparator per level. It is the fastest possible and the cost doubles with every extra bit. Successive approximation tries the most significant bit first, keeps it or discards it, and moves down. It needs one comparator and as many steps as bits, which is the balanced choice for most work. Dual slope charges an integrator from the input for a fixed time, then discharges it at a fixed rate and times how long that takes. It is slow, and it averages the input over the charging time. Choose that time to be a whole number of mains cycles and interference at the mains frequency averages to nothing. That is why dual slope conversion lives inside multimeters.
What you should now be able to explain or do
Explain both 555 modes from the internal comparators and flip flop. Design a monostable for a stated pulse length and an astable for a stated frequency and duty cycle. Describe the feedback loop inside an adjustable regulator. Say why the R-2R ladder is preferred to weighted resistors. Compare flash, successive approximation and dual slope conversion on speed, cost and noise rejection.
Check yourself
Where do the 555's two thresholds come from?
An internal chain of three equal resistors across the supply. It sets the comparators at one third and two thirds of the supply voltage.
Why is a 555 astable output not a square wave by default?
Charging passes through both resistors and discharging through only one. The high time is therefore longer than the low time.
Why is the R-2R ladder preferred to weighted resistors?
It needs only two resistor values however many bits there are. Fabricating many precise, widely different values on one chip is much harder.
Why does a dual slope converter reject mains hum?
It averages the input over its charging time. Make that time a whole number of mains cycles and the interference sums to zero.
When would you accept the cost of a flash converter?
When speed matters more than anything else. It compares against every level at once, and its cost roughly doubles for each extra bit.
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