EC-21.3 Getting a Design onto an FPGA: Synthesis, Placement and Routing

What this is and why it exists

Synthesis is not compilation, and treating it as compilation produces slow, enormous designs.

The tool is matching patterns in your source against the fixed resources the silicon actually contains. A description that ignores those resources still works, and uses ten times the area at half the speed.

So this topic starts with what is physically in the part. Knowing roughly how many lookup tables, flip-flops, memory blocks and multipliers a device holds changes how a person writes hardware description. The change is permanent and welcome.

The vocabulary

• Lookup table — a small memory that implements any function of a few inputs.
• Logic element — a lookup table with a flip-flop and some carry logic beside it.
• Block memory — a dedicated memory built into the device.
• Hard multiplier — a dedicated arithmetic block, faster and smaller than built logic.
• Interconnect — the configurable wiring between logic resources.
• Inference — synthesis recognising a code pattern and using a dedicated resource for it.
• Placement — deciding which physical resource each piece of logic occupies.
• Routing — threading the interconnect to connect placed resources.
• Bitstream — the file that configures every resource in the device.

The mental model

A field-programmable device is a fixed array of small resources plus configurable wiring. It is not a blank slate. Every synthesis decision is an attempt to express your logic in the resources that exist.

Inference is where most surprises live. The tool recognises a shape in your code and uses a dedicated resource for it. A memory written one way becomes a block memory. The same memory with a synchronous reset on the output can become thousands of individual registers instead. The inference report is where you find out which happened, and reading it is not optional.

Placement and routing are the slow part of the flow. What limits a design is usually the interconnect rather than the logic, which surprises most beginners. Congestion in the wiring stops a design fitting while three of the four resource types are nearly empty.

That is why the utilisation report matters. It breaks usage down by resource type, and a failure to fit points directly at the one that ran out. Being short of memory blocks and short of lookup tables call for entirely different changes.

The output of the whole flow is a bitstream: a file that sets every lookup table and every switch in the part. It is loaded at power-up, from a memory on the board or from a cable. Where that file lives, and whether it is protected, is a product decision rather than a design one.

One practical point. Once a design is inside the device, its internal signals are invisible unless you built a way to see them. A synthesised logic analyser core costs resources and is very often the fastest route to an answer. Planning for it before the device is full is worth doing.

What you should now be able to explain or do

• Name the main resource types in a field-programmable device.
• Explain what inference is, and read an inference report to check it happened.
• Say why interconnect congestion limits designs more often than logic capacity.
• Read a utilisation report and identify which resource caused a failure to fit.
• Describe what a bitstream contains and where it is loaded from.
• Plan for in-device visibility before the device is full.

Check yourself