EC-25.6 Electrostatic Discharge, Latch-Up and Failure Analysis
The standard treatment of electrostatic discharge, latch-up and failure analysis: discharge models, on-chip protection, handling, the parasitic structure and root cause work, September 2026
What this is and why it exists
Two hazards destroy working parts in ways nothing in the design intended.
A few thousand volts from a person walking across a floor. And a parasitic device nobody drew, which switches on and does not switch off until the power is removed.
The last third of the topic is different in kind: the business of finding out what actually happened to a part that failed. That is a laboratory skill and an investigative one, and it is the last step in the chain this module has been building.
The vocabulary
- Electrostatic discharge — a sudden transfer of charge into or out of a device.
- Human body model — a discharge from a charged person through a pin.
- Charged device model — a discharge from the part itself into ground.
- Protection structure — on-chip circuitry that conducts a discharge safely away.
- Latent damage — weakening that leaves a part working but short-lived.
- Latch-up — a parasitic structure conducting until power is removed.
- Guard ring — a doped ring that collects stray current and suppresses latch-up.
- Decapsulation — removing a package to expose the die for inspection.
- Root cause — the underlying reason a failure occurred, rather than its location.
The mental model
The standard discharge models represent different sources. A charged person discharging through a pin gives a moderate current with a slow rise. A charged machine gives more. A charged device discharging into ground gives an extremely fast pulse. They differ in rise time and energy, and a part robust against one can be destroyed by another.
Protection works by providing a deliberate path. A structure on every pin turns on faster than the circuit it protects can break. It conducts the discharge to a supply rail, then returns to being invisible. It costs area, and it costs capacitance on the pin, which is why high-speed pins have weaker protection than others.
Latent damage is the reason handling procedures are enforced even when nothing visibly failed. A discharge below the destructive level can weaken an oxide, leaving a part that works today and fails in six months. Nothing at test will find it.
Latch-up is a different mechanism. The layers of a device form a pair of parasitic transistors arranged so that each feeds the other. Once triggered, by overshoot on a pin or by radiation, they conduct until power is removed, often drawing enough current to destroy the part. Prevention is geometric: keep the parasitic gain low, and provide low-resistance paths to the supplies with guard rings and substrate contacts.
Failure analysis is the investigative half. The order matters, because most useful steps are destructive. Characterise electrically first. Image non-destructively next, looking for hot spots or opens. Only then decapsulate, and only then section the die. Doing the destructive steps first destroys the evidence you needed.
The output is a root cause, not a location. A short between two layers is a finding. Why the short was there, and whether other parts share the condition, is the answer that changes anything.
What you should now be able to explain or do
- Distinguish the discharge models and say why one part may survive only some.
- Explain how an on-chip protection structure works and what it costs.
- Say why handling rules apply even when no failure was observed.
- Describe the parasitic structure that causes latch-up and how it is prevented.
- Order the steps of a failure analysis so that evidence survives.
- Distinguish a failure location from a root cause.
Check yourself
Why do high-speed pins often have weaker protection?
Because protection adds capacitance. On a fast pin that capacitance costs performance, so the design accepts a lower discharge rating.
What is latent damage and why is it dangerous?
Weakening below the destructive level. The part passes every test and fails months later, so the problem escapes into the field undetected.
What stops latch-up once it starts?
Removing the power. The parasitic pair sustains its own conduction, so nothing short of interrupting the supply will turn it off.
Why is the order of failure analysis steps important?
Because most useful steps are destructive. Electrical and non-destructive imaging must come first, or the evidence is gone before it is examined.
Go deeper
We haven't checked most of these for screen reader use yet.
Back to Electrostatic Discharge, Latch-Up and Failure Analysis: work through the checklist