EC-25.6 Electrostatic Discharge, Latch-Up and Failure Analysis
You can explain how on-chip protection conducts a discharge away from the circuit it protects, describe the parasitic structure that causes latch-up and the layout rules that prevent it, and lay out a failure analysis from a returned part to a root cause.
Before:PE1-1. VLSI TechnologyEC-8. Measurements, Instrumentation and Experimental MethodEC-21. Hardware Verification, FPGA and SoC Design
Two hazards deserve their own topic because they destroy working parts in ways nothing in the design intended: a few thousand volts from a person walking across a floor, and a parasitic device nobody drew that switches on and does not switch off. The last third of the topic is the discipline of finding out what actually happened to a part that failed, which is a laboratory skill and an investigative one.
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Discharge models, and what each one represents
The standard models represent a charged person, a charged machine and a charged device discharging through a pin, and they have very different rise times and energies. A part robust against one can be destroyed by another.
NPTEL: Basic Overview of Semiconductor Device Processing and IC Fabrication (IIT Kanpur) · CourseOn-chip protection: a deliberate conduction path around the circuit
Protection works by providing a route that turns on faster than the thing it protects can break, and returns to being invisible afterwards. Every input and output pin has one, and it costs area and capacitance.
NPTEL: Semiconductor Device Modeling and Simulation (IIT Kharagpur) · CourseHandling: wrist straps, ionisers and why an undamaged part may already be weakened
A discharge below the destructive level can leave a part that works and fails early, which is invisible at test. That is why handling procedures are enforced even when nothing has visibly gone wrong.
Latch-up: the parasitic structure nobody drew
The layers of a device form a pair of parasitic transistors that can latch into a conducting state and stay there until power is removed, drawing enough current to destroy the part. It is triggered by overshoot on a pin or by radiation.
NPTEL: Semiconductor Device Modeling and Simulation (IIT Kharagpur) · CourseGuard rings, substrate contacts, and the layout rules that prevent it
Preventing latch-up is largely a matter of keeping the parasitic gain low and providing low-resistance paths to the supplies. The rules are geometric and are checked automatically.
Failure analysis: from a returned part to a root cause
Electrical characterisation, then non-destructive imaging, then decapsulation and microscopy narrow a failure from a symptom to a location to a mechanism. Doing the destructive steps first destroys the evidence.
NPTEL: Introduction to Reliability Engineering (IIT Kharagpur) · Course
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- FreeNPTEL / IIT Kanpur · CourseNPTEL: Basic Overview of Semiconductor Device Processing and IC Fabrication (IIT Kanpur)
- FreeNPTEL / IIT Kharagpur · CourseNPTEL: Semiconductor Device Modeling and Simulation (IIT Kharagpur)
- FreeNPTEL / IIT Kharagpur · CourseNPTEL: Introduction to Reliability Engineering (IIT Kharagpur)
Links last checked 4 Sept 2026.
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