S5-4.5 Combinational, Sequential Circuits & Memories
You can design logic functions with decoders and multiplexers, build serial, parallel and BCD adders and asynchronous and synchronous counters with real ICs, and describe ROM and RAM architectures, PAL, PLA, CPLD and FPGA.
The shift from the earlier digital design course is that here the building blocks are catalogue parts with part numbers - an IC7493 ripple counter and an IC74163 synchronous counter behave differently in ways the datasheet, not the theory, tells you. Expanding word size and capacity is the practical memory skill: combining small chips into the array you actually need. PLDs close the unit by inverting the whole approach - instead of wiring fixed parts together, you configure one part to become the logic, and FPGA is where that idea ends up.
Work through these
Design of logic functions using decoders
Using a decoder as a general logic element rather than an address selector. It is a change of perspective more than a new device, and it makes the next item easier.
Design of logic functions using multiplexers
The same trick with a multiplexer, and the more useful of the two. Being able to implement an arbitrary function this way is a genuinely handy skill.
Serial adder, parallel adder and BCD adder
Three adders trading speed against hardware, which is the same axis as everywhere else in this subject. The decimal version exists because humans want decimal answers.
Asynchronous counter using IC7493
A counter built from a real catalogue part, with the ripple delay that comes with it. The datasheet, not the theory, tells you how it actually behaves, which is the shift this whole topic represents.
Synchronous counter using IC74163
The synchronous alternative, where every stage clocks together. Comparing the two counters on the same task is what shows you why the extra logic is worth it.
Memory terminology; ROM and RAM types
The vocabulary, and the differences between the types that actually change a design. Settle this before the architecture items below.
Memory architectures and operation
How a memory is organised internally, and what a read or write actually does. It explains the timing numbers you would otherwise copy without understanding.
Expanding memory word size and capacity
The practical skill: combining small chips into the array you actually need, in width and in depth. Almost every real design does one or the other.
Introduction to PLDs: PAL and PLA; programming with PLDs
The devices that invert the whole approach: instead of wiring fixed parts together, you configure one part to become the logic. This is where the topic stops being about catalogue parts.
Introduction to CPLD and FPGA and their architectures
Where that idea ends up, and the technology most of you will actually use. Treated as an introduction, and picked up properly in the design subjects.
Lab: implement logic functions using decoders and multiplexers
The bench version of the first two items. Implementing the same function both ways in one session is what makes the choice between them meaningful.
Lab: implement binary adder/subtractor and BCD adder using ICs
The bench version of the adders, with real parts and real propagation delays. The carry path is where the delay lives, which is easier to believe once measured.
Lab: design synchronous and asynchronous up/down counters; shift registers and ring counter
The bench version of the counters and registers, in both directions. Building the shift register and the ring counter from the same parts shows how small the difference is.
Lab: interface counters with 7-segment LED display units
The item that makes the rest visible: a display you can read. Interfacing is where timing and drive current stop being abstract.
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