S4-4.4 Verilog HDL: Gate & Dataflow Modelling

Work through these

• VLSI design flow overview

  The route from a design idea to a manufactured or configured chip, with the standard stages named. Knowing the flow tells you what each later tool is for and where in the process your own work sits.

• Verilog basics: data types, system tasks, compiler directives

  The vocabulary of the language: what a wire is, what a register is, and how to make a simulation report what it is doing. Verilog data types are not programming variables, and treating them as such causes the first round of confusion.

  HDLBits: Verilog Practice Problems · Tutorial

• Gate-level modelling: gate types and delays

  Describing a circuit as the gates it is made of, with delays attached, which maps most directly onto the schematics from earlier units. It is the gentlest on-ramp because you already know the circuits.

• Dataflow modelling: continuous assignment and delays

  Dataflow modelling describes what the outputs continuously equal rather than which gates produce them. It is the level at which most combinational hardware is actually written.

• Design of a stimulus block (testbench)

  A stimulus block feeds a design its inputs and checks what comes out, and in real projects writing it is half the work. Treating the testbench as an afterthought is the standard route to a design nobody trusts.

• Lab: write and simulate gate-level and dataflow versions of the same circuit

  Write the same circuit twice, once at gate level and once as dataflow, and simulate both. Seeing one circuit under two descriptions is what makes the levels of abstraction concrete.