S5-3.5 DSP Processors

What this is and why it exists

Signal processing spends nearly all its time in one short loop. Multiply a sample by a coefficient, add the result to a running total, fetch the next sample, repeat.

A general purpose processor runs that loop adequately. A processor shaped around it runs it far better. This topic is about what that shaping looks like.

The vocabulary

• Multiply-accumulate — a single operation that multiplies two values and adds the product to a total.
• Harvard architecture — separate paths for instructions and data, so both can be fetched at once.
• Functional unit — one of several arithmetic units that can work in the same cycle.
• Very long instruction word — an instruction that tells several functional units what to do at once.
• Pipeline depth — how many stages an instruction passes through before it completes.
• Linear addressing — an address pointer that moves straight through memory.
• Circular addressing — a pointer that wraps back to the start of a buffer automatically.
• Delay line — the stored history of recent samples that a filter works on.
• Code Composer Studio — the development environment for this processor family.
• DTMF — dual tone multi frequency, the pair of tones a telephone keypad sends.

The mental model

Read the architecture as filter-shaped and every feature becomes a consequence.

The inner loop needs a multiply and an add every sample, so the hardware provides them as one operation. It needs a sample and a coefficient in the same cycle, so there are separate memory paths rather than one. Fetching an instruction must not compete with fetching data, so instruction and data paths are separate too.

Several functional units then let more than one operation start per cycle. A long instruction word tells them all what to do together, which moves the scheduling work from the hardware into the compiler. That keeps the chip simple and fast, and it makes the compiler's job harder.

Deep pipelining is how the clock rate is reached. It is the same idea as in computer architecture, pushed further. It also has a cost that shows in the programming model. A result is not available immediately after the instruction that computes it, and a jump costs more the deeper the pipeline is. Those awkward edges are the price of the clock rate.

The registers decide how much of a filter can stay inside the processor. Fetching from memory costs cycles, so a filter whose working set fits in registers runs far faster than one that does not. The register list is dry to read and it decides real performance.

Circular addressing is the clearest example of the whole idea. A filter keeps a delay line, which is a fixed-size buffer of recent samples. Every new sample must go in, and the oldest must fall out. Written as ordinary code that means checking the pointer against the end of the buffer, every sample, forever. So the hardware provides a pointer that wraps by itself. The test disappears, and with it a jump that would have disturbed the pipeline every time round the loop. One addressing mode removes work from the innermost loop in the subject.

Linear addressing is the ordinary mode beside it, for data that is walked through once rather than cycled.

The laboratory work follows from all of this. Getting the toolchain running in real time is the step everything else depends on. It costs a whole session if it is left until last. Tone generation is a good first project because you can hear at once whether it is right.

What you should now be able to explain or do

State the inner loop that shapes these processors. Explain why separate instruction and data paths and a multiply-accumulate unit follow from it. Say what several functional units and a long instruction word move onto the compiler. Describe the cost of a deep pipeline in the programming model. Explain what circular addressing removes from a filter's inner loop, and why that matters more than it first appears.

Check yourself