S5-2.3 CPU & Input-Output Organization

What this is and why it exists

The previous topic built a machine that works. This one asks how to make it fast, and how to connect it to the world outside.

Both halves turn out to be the same question asked twice. How much of the work can happen at the same time as other work?

The vocabulary

• General register organization — working values held in a set of interchangeable registers.
• Stack organization — working values held on a stack, with operations acting on the top of it.
• Instruction format — the layout of an instruction: what the operation is and where its operands are.
• Addressing mode — the rule that turns the address field of an instruction into a real address.
• CISC — a design with many instructions, some of them doing a great deal of work each.
• RISC — a design with few, simple, fixed-length instructions, executed quickly.
• Pipelining — overlapping the stages of consecutive instructions.
• Hazard — a situation that stops the next instruction entering the pipeline on time.
• Programmed input and output — the processor waits for a device by testing it repeatedly.
• Interrupt initiated transfer — the device signals the processor when it is ready.
• DMA — direct memory access. A controller moves data without the processor in the path.
• Daisy chain — priority decided by the order devices are wired in.

The mental model

Start with where working values live. A general register machine keeps them in interchangeable registers, so an instruction names the ones it wants. A stack machine keeps them on a stack, so operations take their operands from the top and put results back there. The second explains how expressions are evaluated and how procedure calls save their state, so it is worth understanding even on a register machine.

Instruction formats and addressing modes are the part a programmer actually feels. A format says how many operands an instruction names and how wide each field is. An addressing mode says how to read those fields. The operand may sit in the instruction itself, or in a register. It may sit at an address held in a register, or at an address computed by adding an offset. The same list returns when you meet a specific processor, so effort here is repaid.

CISC and RISC is the long argument of processor design. State it in terms of decoding and it stops being a list. A CISC machine offers powerful, variable-length instructions, so the hardware must do a lot of work to find out what each one wants. A RISC machine offers few, fixed-length, simple instructions, so decoding is trivial and the hardware can be made fast and regular. Both sides won something, and modern processors take from each.

Pipelining is the idea that pays. Split instruction handling into stages, then let each stage work on a different instruction at the same time. No single instruction finishes any sooner. What rises is throughput, because a result emerges every cycle instead of every few cycles. Hazards are what make it interesting. An instruction may need a result the one ahead has not produced yet. A jump may mean the instructions already fetched are the wrong ones. Both cost cycles.

Now cross to the outside world. A peripheral is slow, and it speaks its own language, so an interface stands between it and the processor. The processor reaches that interface in one of two ways. Addresses set aside for devices give isolated input and output. Ordinary memory addresses give memory mapped input and output. The first spends instruction encoding space on special instructions. The second spends address space. Which one a machine chose is visible in its instruction set.

The three transfer modes form a ladder of processor involvement. In programmed transfer the processor tests the device again and again until it is ready, which burns cycles doing nothing. With interrupts the processor gets on with other work and the device asks for attention when it is ready. With direct memory access a separate controller moves the data between the device and memory, and the processor is out of the path entirely. Rank them by how much of the processor's time they consume and the three stop blurring together.

Priority closes the topic. When several devices interrupt at once, something must choose. A daisy chain wires the devices in order and passes the grant along, so the nearest device wins. It is cheap and slow. A parallel priority circuit decides in one step using more hardware. That is the same trade as everywhere else here: speed bought with hardware.

What you should now be able to explain or do

Compare general register and stack organization, and say what each one makes straightforward. Read an instruction format and apply its addressing modes. State the CISC and RISC comparison in terms of what the hardware must decode. Explain why pipelining raises throughput without shortening any single instruction, and name two kinds of hazard. Rank programmed transfer, interrupts and direct memory access by processor involvement, and compare daisy chained with parallel priority.

Check yourself