S5-2.3 CPU & Input-Output Organization

Work through these

• General register organization and stack organization

  Two ways of holding working values, and the reason instruction sets look the way they do. Stack organization also explains how procedure calls and expression evaluation work underneath.

• Instruction formats and addressing modes

  How an instruction says what to operate on, which is the part of an instruction set a programmer actually feels. Addressing modes come back in the microprocessor topic, so time here is repaid.

• Data transfer and manipulation; program control

  The bulk of what a machine can be asked to do, taken as a group. Program control is the interesting half, because a conditional jump is where the sequential model finally bends.

• CISC and RISC: features and comparison

  The long running argument in processor design, and one where both sides won something. State the comparison in terms of what the hardware has to decode and it stops being a list of bullet points.

• Instruction pipeline

  The idea that pays: overlap the stages of consecutive instructions and throughput rises without any single instruction getting faster. That is also why hazards become the interesting problem.

• Peripheral devices and the I/O interface

  Where the processor meets the world, and the layer of translation each device needs. It sets up the three transfer modes below.

• I/O bus and interface modules; isolated versus memory mapped I/O

  Two ways to address a device, and the trade between spending instruction encoding space and spending address space. Which one a machine chose is visible in its instruction set.

• Modes of transfer: programmed I/O, DMA, interrupt initiated I/O

  A ladder of how much the processor is involved: it burns cycles waiting, it gets interrupted, or it steps out of the data path entirely. Rank them by that and the three stop blurring together.

• Priority interrupt: daisy chaining and parallel priority interrupt

  Priority implemented in wiring rather than software, which is worth seeing once. Daisy chaining is cheap and slow, and the parallel version buys speed with hardware, which is the same trade as everywhere else in this subject.