S4-4.5 Verilog: Behavioral Modelling & Synthesis

What this is and why it exists

Behavioral Verilog is where the language becomes expressive — always blocks, if-else, case, loops — and where beginners write beautiful code that describes no buildable hardware. The whole unit balances on one habit: for every construct, ask what hardware it implies. The blocking versus non-blocking assignment rule is the classic trap with a two-line cure, and the unit ends by closing the loop: what synthesis actually does with your text, and how a bitstream turns an FPGA into your circuit by evening.

The vocabulary

• initial and always — the two procedural blocks: initial runs once (testbench territory), always re-runs whenever its sensitivity list triggers (the shape of real hardware).
• Blocking assignment (=) — executes in sequence within the block, each result visible to the next line; the idiom for combinational logic.
• Non-blocking assignment (the <= form) — right-hand sides all read first, left-hand sides all updated together at the clock; the idiom for sequential logic.
• Sensitivity list — what wakes an always block: a clock edge for sequential logic, every read signal (the star form) for combinational.
• Tasks and functions — named reusable procedures; functions compute combinationally in zero simulated time, tasks may contain timing.
• Switch-level modelling — describing circuits as networks of MOS transistor switches; below gates, near the silicon.
• Logic synthesis — the compiler for hardware: RTL text into an optimised gate netlist against a cell library and timing constraints.
• FPGA — a fabric of configurable logic blocks and routing, programmed by a bitstream into any modest digital design; the way student designs meet reality.

The mental model

An always block is a machine that re-decides its outputs every time its triggers fire. Written with a clock-edge trigger and non-blocking assignments, it is a bank of flip-flops: everything on the right-hand sides is read at the edge, then every left-hand side updates at once — which is exactly how real registers clock, and why two registers can swap values in two non-blocking lines with no temporary. Written with a star sensitivity list and blocking assignments, it is a cloud of gates re-evaluated whenever an input moves. The two-line rule — combinational: blocking; sequential at the clock: non-blocking — is not style, it is a description of physics, and mixing them produces simulations that disagree with the synthesised silicon: the worst kind of bug, the one that appears only after the design looks finished.

The hardware question governs every other construct too. An if without an else, in combinational code, implies "otherwise hold the old value" — that is a latch, usually unintended (the lint-famous inferred latch). A for loop does not iterate in time; it unrolls into copies of hardware. Case statements become multiplexers. Functions are combinational bundles; tasks suit testbenches. Switch-level modelling sits below all this — circuits as MOS switch networks — worth one look so the gate abstraction has a floor under it.

Synthesis is the payoff and the honesty check: the tool reads your RTL, infers registers and logic, optimises against a cell library and your timing constraints, and emits a netlist — the automated descendant of the hand minimization from the first unit. For an FPGA, placement and routing then map that netlist onto the chip's logic blocks, and the bitstream configures it: your FSM from the sequential unit, described behaviourally, synthesised, and blinking on a board the same day. That text-to-working-silicon loop is the skill that later carries edge-AI deployment — putting trained models onto FPGAs begins exactly here.

What you should now be able to explain or do

State the blocking/non-blocking rule and the failure mode of breaking it. Spot an inferred latch in combinational code and repair it. Predict the hardware for an if-else chain, a case statement and a for loop. Describe what synthesis consumes and emits, and walk your Unit-3 FSM from behavioural text to a simulated, synthesisable design.

Check yourself