EC-10.5 More Than One Core
You can say why processors gained cores instead of speed, describe what threads share and what they do not, explain cache coherence and memory ordering in outline, and name the cases where another core does not help at all.
Before:S5-2. Computer Architecture and MicroprocessorsUnlocks:S5-3. Digital Signal Processing
Every device a reader of this module will build software for has several cores, and the consequences reach all the way down to a microcontroller with two. This topic is deliberately an outline rather than a course in parallel programming, because its purpose is to make the reader able to ask the right question rather than to answer all of them.
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Why cores multiplied instead of getting faster
Two cores at a lower clock use less power than one at twice the rate, so once heat became the limit, more cores was the only remaining move. The cost was pushed onto software, where it still sits.
NPTEL: Multi-Core Computer Architecture (IIT Guwahati) · CourseThreads, processes and what is shared
Threads in one process share memory and can corrupt each other's data; separate processes do not and must be given a channel. The choice is a trade between the cost of communication and the cost of mistakes.
NPTEL: Multi-Core Computer Architecture (IIT Guwahati) · CourseCache coherence, in outline
Each core has its own cache, so the same address can sit in several of them. Coherence hardware makes them agree, and the traffic it generates is why two cores writing to nearby addresses can be slower than one.
NPTEL: Multi-Core Computer Architecture (IIT Guwahati) · CourseThe memory model, and reordering you did not write
Compilers and processors both reorder memory operations when the result looks the same to one core. To another core it does not look the same, which is why a memory model has to state what is guaranteed.
NPTEL: Computer Architecture (IIT Delhi) · CourseLocks, atomics and the cost of agreement
A lock makes cores take turns, and an atomic instruction does one small update indivisibly. Both work by forcing agreement between caches, and both are far more expensive than the instruction they replace.
NPTEL: Multi-Core Computer Architecture (IIT Guwahati) · CourseWhere a second core does not help
Work that is one long chain of dependent steps, or limited by memory bandwidth rather than by computation, gains nothing. Recognising these before writing parallel code saves the effort of proving it the hard way.
NPTEL: Multi-Core Computer Architecture (IIT Guwahati) · Course
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