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S4-1.2 JFET Biasing & Amplifiers

Standard analog-electronics theory — written August 2026

What this is and why it exists

The JFET retells the BJT story with one big change of driver: current in a BJT is set by a base current, in a JFET by a gate voltage, with almost no gate current at all. That buys enormous input resistance and costs you predictability — JFET parameters spread even more widely than beta does. This lesson is the BJT unit run again for a voltage-controlled device, and the parallels carry most of the load.

The vocabulary

  • Pinch-off voltage (Vp) — the gate-source voltage at which the channel closes and drain current stops.
  • IDSS — the drain current with the gate shorted to the source; the device's maximum, and a heavily spread parameter.
  • Self-bias — a source resistor develops a voltage that reverse-biases the gate automatically; no second supply needed.
  • Zero-current-drift bias — choosing the operating point where two opposing temperature effects cancel, so drain current barely moves with temperature.
  • Transconductance (gm) — how much drain current changes per volt of gate-source change; the gain-setting parameter of the small-signal model.

The mental model

A garden hose under your thumb. The channel is the hose, the gate voltage is your thumb: press harder (more negative gate) and the flow shrinks toward pinch-off. Nothing flows into your thumb — that is the near-infinite gate resistance — but how hard each device needs pressing varies from part to part, which is why fixed gate bias is even less trustworthy here than fixed base bias was for the BJT.

Self-bias is the elegant fix: the device's own source current generates its own reverse gate bias, so a device that runs hot on current presses its own thumb harder. Zero-current-drift bias is the exam favourite with a real lesson inside: mobility falls with temperature (current down) while the pinch-off characteristic shifts (current up), and there is one bias point where the two cancel. Precision circuits are routinely built at such cancellation points.

The amplifier configurations mirror the BJT exactly: common source is common emitter (gain, inversion), common drain is common collector (the source follower, a buffer), common gate is common base (low input resistance, good at high frequency). The small-signal model is leaner — a current source of gm times the gate-source voltage, with a drain resistance across it — so the analysis runs faster, and gm times the drain load is the gain estimate you reach for first.

What you should now be able to explain or do

Bias a JFET by self-bias given IDSS and Vp, and say why fixed bias is risky. Explain zero-current-drift biasing as two cancelling temperature effects. Analyse CS, CD and CG stages with the small-signal model and map each onto its BJT cousin. Predict which spreads more between parts: a self-biased or a fixed-bias Q-point.

Check yourself

Almost nothing — the reverse-biased gate draws nanoamps, so the JFET presents an enormous input resistance where the BJT demands real base current.

The source resistor converts the device's own current into reverse gate bias: a part that tends to conduct more generates more opposing bias, pulling all parts toward similar operating points.

Carrier mobility falling with temperature, which lowers drain current, and the shift of the pinch-off characteristic with temperature, which raises it — at one operating point the two balance.

Common source is common emitter, common drain (source follower) is common collector, common gate is common base — same roles: gain stage, buffer, high-frequency stage.

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