S5-3.4 Finite Word Length Effects & Multirate DSP

Work through these

• Quantization errors: round-off and truncation

  Where the mathematics meets a processor with a fixed number of bits. A filter that was perfect on paper starts misbehaving here, and this topic is about why.

• Limit cycles

  The memorable case: a stable filter with zero input can oscillate forever, purely because of rounding. No continuous domain analysis would ever predict it, which is the point.

• Overflow oscillations

  The other way finite arithmetic bites, when a sum exceeds what the register can hold. Saturation against wraparound is a design decision with very different failure behaviour.

• Coefficient quantization error

  The coefficients are stored in finite precision too, so the filter you built is not quite the filter you designed. Sensitivity to this is one of the reasons structure choice matters.

• Introduction to multirate digital signal processing

  The practical half of the topic: changing sample rate deliberately, rather than treating it as fixed. It underlies converters, audio equipment and communication receivers alike.

  NPTEL: Digital Signal Processing and its Applications · Course

• Decimation by a factor D

  Throwing samples away, and the filtering you must do first to avoid aliasing. The order of the two operations is the thing people get wrong.

• Interpolation by a factor I

  The mirror operation: inserting samples and filtering to fill them in properly. Together with the item above it covers any integer rate change.

• Sampling rate conversion by a rational factor I/D

  Combining the two to reach a ratio that is not an integer. The order matters, and working out why is a good check that the previous two items landed.

• Noble identities

  The rearrangements that let you move a filter through a rate change. They look like algebraic tricks and they are what makes efficient multirate design possible.

• Design of a multistage decimator

  The practical payoff: doing a large rate change in stages is dramatically cheaper than doing it in one. This is the item that justifies everything above it.

• Lab: interpolation and decimation, and multistage filter design in MATLAB

  The bench version of the multirate half. Building the multistage design and comparing its cost against the single stage version makes the saving concrete.

• Lab: decimation and interpolation on the DSK

  The same work on a real processor, where the cost saving above shows up as cycles you actually have or do not have.