EC-10.3 ARM and RISC-V, Read Side by Side

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What this is and why it exists

One instruction set taught alone leaves a reader unable to tell a design decision from a law of nature.

Two, read against each other, make every choice visible as a choice. That is the whole reason this topic is a comparison rather than a course on one architecture.

These two are chosen because between them they run almost everything a graduate of this area will meet. That runs from a sensor node on a battery to a data centre.

The vocabulary

  • General-purpose register — a register usable for any value, as opposed to one with a fixed role.
  • Load-store architecture — a design where arithmetic operates only on registers.
  • Addressing mode — a way of forming a memory address from registers and constants.
  • Condition flags — bits recording the result of a comparison, used by later instructions.
  • Extension — an optional set of instructions added to a base instruction set.
  • Profile — a named collection of extensions that implementations may target.
  • Compressed encoding — shorter forms of common instructions, used to reduce program size.
  • Architecture reference manual — the definitive specification of an instruction set.

The mental model

Build the comparison table yourself. That is the exercise, and reading someone else's table is not a substitute.

Four or five rows are enough to make the two designs distinct. How many general-purpose registers, and how wide. Whether instructions are all one length. How a comparison result is carried to the instruction that uses it. How a function returns. That last one is more revealing than it sounds.

Registers come first because everything else refers to them. Both designs keep a modest bank of general registers, in the region of sixteen to thirty-two. A few are reserved by convention for the stack pointer, the return address and argument passing.

The reservations are agreements, not hardware, and they differ. That is exactly the calling convention idea from the boundary topic, now met in two concrete forms, which is what makes it stick.

Both are load-store designs, and this is the most consequential shared decision. Arithmetic instructions take their operands from registers only, and memory is reached by explicit load and store instructions.

The reason is pipelining. If every instruction may touch memory, every instruction has an unpredictable duration, and a regular pipeline becomes impossible. Restricting memory access to two instruction types makes the timing of everything else predictable.

The visible consequence, once you have read compiled code, is how much of it is moving values between registers and memory. That movement is not waste. It is the price of the regularity that makes the machine fast.

Addressing modes are where the budget is spent. A base register plus a small constant covers most real code, and an index register covers arrays. Each additional mode costs encoding space in every instruction word and costs hardware in the address unit.

Comparing the two designs' lists shows a real difference in philosophy. It makes the point that a shorter list is a decision rather than a limitation.

Extensions and profiles are how a modern instruction set grows without breaking anything. Floating point, vector operations and compressed encodings are optional, gathered into named profiles that implementations can target and compilers can assume.

One point deserves care because it is widely misunderstood. Open, for an instruction set, means the specification can be implemented without a licence. It does not mean any particular chip is free, open-hardware, or even publicly documented. Getting that distinction right is part of understanding the industry rather than the technology.

Finally the reference manuals, which are thousands of pages and are written to be searched rather than read. The skill worth practising is finding one instruction and answering three questions about it. How it is encoded, exactly what it does to registers and flags, and what exceptions it can raise.

Doing that five times for five instructions is more useful than reading a hundred pages in order. It also transfers directly to every datasheet in the embedded module, where the same skill is what turns a wall of tables into an answer.

What you should now be able to explain or do

  • Build a comparison table of two instruction sets from their own reference material.
  • Describe the register conventions of each and connect them to the calling convention idea.
  • Explain why a load-store design makes pipelining practical, and what it costs in code.
  • Discuss addressing modes as a budget rather than as a feature list.
  • Say precisely what open means for an instruction set, and what it does not mean.
  • Find and read one instruction's encoding, effect and exceptions in a reference manual.

Check yourself

Because an instruction that may touch memory has an unpredictable duration. Restricting memory access to loads and stores makes the timing of every other instruction regular enough to pipeline.

No. It is the cost of the load-store restriction, which buys the pipeline regularity that makes the processor fast in the first place.

That the specification may be implemented without paying for a licence. It says nothing about whether a particular chip is free, documented, or open in any other sense.

By searching it for one instruction at a time and answering how it is encoded, what it changes, and what exceptions it raises. These documents are references, not textbooks.

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