11.8 Accelerators: GPU, NPU, FPGA
You can read a hardware spec sheet and know what it means for your model.
Before:06. Deep Learning
Reading an accelerator spec sheet — GPU memory hierarchies, NPUs, FPGA inference — tells you what a model will actually cost to run on given silicon, and roofline thinking sorts compute-bound from memory-bound workloads. It closes the bridge module at the hardware boundary. The comparison trap is peak TOPS: unreachable peaks are marketing, memory bandwidth is usually the real ceiling, and the roofline makes that visible before the purchase order does.
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GPU memory hierarchy and occupancy
How memory is arranged on an accelerator and how much of it is being used productively. Most disappointing performance comes from memory movement rather than arithmetic.
NPUs and mobile accelerators
Dedicated inference processors in phones and embedded devices, with their own constraints on what operations they support. A model using an unsupported operation falls back to something much slower.
FPGA inference: when it is worth it
Reconfigurable hardware for inference, which pays off for high-volume fixed workloads with tight latency requirements. Knowing when it is worth the development cost is the judgement here.
Roofline thinking: compute-bound vs. memory-bound
A simple model that predicts whether performance is limited by computation or by memory bandwidth. It tells you which optimisation will actually help before you attempt any.
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